Description
The ASD5010 is a versatile
high performance low power analog-to-digital converter (ADC), with
interleaving modes to increase sampling rate. Integrated Cross Point
Switches activate the input selected by the user. In single channel
mode, one of the A, B, C or D inputs can be selected as valid input to
the 8-bit 1 GSPS ADC. In dual channel mode, any two of the channels
A, B, C or D can be selected as valid inputs to the two 8-bit 500 MSPS
ADCs. In four channel mode, all 4 inputs are assigned to an 8-bit 250
MSPS ADC.
The
ASD5010 is based on a proprietary structure, and employs internal
reference circuitry, a serial control interface and serial LVDS output
data. Data and frame synchronization clocks are supplied for data
capture at the receiver. Internal 1 to 50X digital coarse gain with
ENOB > 7.5 up to 16X gain, allows digital implementation of
oscilloscope gain settings. Internal digital fine gain can be set
separately for each ADC to calibrate for gain errors. Various modes and
configuration settings can be applied to the ADC through the serial
control interface (SPI). Each channel can be powered down independently
and data format can be selected through this interface. A full chip
idle mode can be set by a single external pin. Register settings
determine the exact function of this pin.
ASD5010 is designed to easily interface with Field Programmable Gate Arrays (FPGAs) from several vendors.
Contact ASD for Preliminary Datasheet
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Features
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Multiple
operational modes
Four channel, 8 bit, up to 250 MSPS
Two channel, 8 bit, up to 500 MSPS
One Channel, 8 bit, up to 1 GSPS
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Integrated Crosspoint Switch
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1x - 50x (0 - 34dB) Digital Gain
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1x gain: 49.5 dB SNR. 16x gain: 46.5dB
SNR
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Ultra Low
Power Dissipation 754 mW including I/O at 1 GSPS
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Designed
for input frequencies up to Nyquist
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Internal
reference circuitry with no required
external components
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0.5
µs startup time from Sleep Mode
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15
µs startup
time from Power Down Mode
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Digital fine gain adjustment for
each ADC
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Internal
Offset Correction
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1.8
V supply voltage
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1.7 - 3.6
V CMOS logic on control
interface pins
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Serial
LVDS output
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7mm x 7mm 48 pin QFN
package
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Functional
Block Diagram

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