Description
ASD1000
is a high performance low power octal analog-to-digital converter
(ADC). The ADC is based on a proprietary structure and employs internal
reference circuitry, a serial control interface and serial LVDS output
data. Data and frame synchronization output clocks are supplied for
data capture at the receiver. Various modes and configuration settings
can be applied to the ADC through the serial control interface (SPI).
Each channel can be powered down independently and data format can be
selected through this interface. A full chip idle mode can be set by a
single external pin. Register settings determine the exact function of
this external pin. There are two options for the serial LVDS outputs,
12- bit or 14-bit. In 12-bit mode, the LSB bit from the ADCs are
removed in the output stream. In 14-bit mode, a '0' is added in the LSB
position. ASD1000 is designed to easily interface with
field-programmable gate arrays (FPGAs) from several vendors. The very
low start up times for ASD1000 allows significant power reduction in
duty-cycled systems, by utilizing the Sleep Modes or Power Down Mode
when the receive path is idle.
Full
Datasheet
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