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ASD0500

Dual Ultra Low Power 20/40/65/80 MSPS, 13/12-bit Analog-to-Digital Converter
Description
The ASD0500 is a high performance low power dual analog-to-digital converter (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. Several idle modes with fast startup times exist. Each channel can independently be powered down and the entire chip can either be put in Standby Mode or Power Down mode. The different modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The ASD0500 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs.

pdficon Full Datasheet
Features

  • 13-bit resolution

  • 20/40/65/80 MSPS versions available

  • Ultra Low Power Dissipation: 30/55/85/102 mW

  • 72 dB SNR at 8 MHz FIN

  • Internal reference circuitry with no required external components

  • 1.8 V core supply voltage

  • 1.7 – 3.6 V I/O supply voltage

  • Parallel CMOS output

  • 64 pin QFN and TQFP package

  • Dual channel

  • Pin compatible with ASD0400

 Functional Block Diagram

Block Diagram
Applications
  • Handheld Communication, PMR, SDR

  • Medical Imaging

  • Portable Test Equipment

  • Digital Oscilloscopes

  • Baseband / IF Communication

  • Video Digitizing

  • CCD Digitizing

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